The present invention relates generally to memory cell arrays, and more particularly to memory cell arrays that use conducting transistors in saturation to write data.
As memory cells are reduced in size with each new generation, soft errors caused, for example, by alpha particles or cosmic rays, become a major concern. One method of providing high soft error immunity is to operate the memory cells in transistor saturation. However, in order to write data into such memory cells, the saturation capacitance in the memory cell transistors must first be discharged. In the prior art, such a capacitive transistor-saturation discharge is achieved by means of increased power and/or delay. Typically, the new data signals themselves are used to overcome this saturation. This discharging requirement thus places a lower limit on the word line voltages that may be used and increases the write times for the cells.
The word line voltage limitation is particularly a acute for Schottky-coupled memory cells operating in deep saturation. In this regard, in order to guarantee that the coupling Schottky diodes for an unselected memory cell do not conduct, the lower word line used in such cells must be set at a predetermined voltage level. However, for deep saturation operation a significant part of the total cell current flows through the load resistor connected to the base of the saturated conducting transistor. Accordingly, the voltage drop across the cell (the drop across that load resistor plus the Vbe for the conducting transistor) is relatively high. Thus, the upper word line for the cell must be set at a comparable level. The result of the above is that the standby current through the memory cell when it is not selected (the current flowing through the load resistors) is on the order of 60 .mu.A. The total standby current on a given upper word line is this memory cell standby current multiplied by the number of cells on that word line. In order to draw such a word line standby current while maintaining the word line voltage level requires that the power supply connection to the upper word line utilize only a small valued resistor therein. However, such a small value resistor directly impacts the WRITE time for the circuit and causes a significantly increased power dissipation for the array. The resulting current sinking requirements placed on adjacent circuits (decoders, etc.) cause cell-to-cell voltage variations, with attendant cell WRITE time variations.
The invention as claimed is intended to remedy the above-described WRITE time and power dissipation problems in saturated memory cell configurations.